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Verilog Design Flow
作者
billchen1020
· GitHub ↗
· v1.2.0
· MIT-0
282
总下载
0
收藏
1
当前安装
3
版本数
在 OpenClaw 中安装
/install verilog-design
功能描述
Design, implement, and verify Verilog/SystemVerilog modules with spec-driven development, self-checking testbenches, and automated simulation workflows. Supp...
安全使用建议
This skill appears coherent for Verilog simulation and VCD analysis, but take these precautions before running it: (1) Inspect testbench and RTL files you run — simulators and Verilog $system calls can execute host commands. The references show an example using $system("python3 check_vcd.py ...") which will run whatever Python is on the host. (2) Install runtime dependencies yourself (e.g., pip install vcdvcd in a virtualenv) and verify you have a trusted simulator. (3) Run simulations in a restricted/sandboxed environment if you’re running untrusted code. (4) The skill doesn’t auto-install packages or fetch remote code; if you see any attempt to download/execute from unknown URLs, treat that as suspicious.
功能分析
Type: OpenClaw Skill
Name: verilog-design
Version: 1.2.0
The skill bundle provides a legitimate and well-structured workflow for Verilog and SystemVerilog design, simulation, and verification. It includes a bash script (scripts/simulate.sh) to automate the use of standard EDA tools like Synopsys VCS, Cadence Xrun, and Icarus Verilog, and a Python script (scripts/check_vcd.py) for waveform analysis using the 'vcdvcd' library. All instructions and code logic are strictly aligned with the stated purpose of hardware development, with no evidence of malicious intent, data exfiltration, or prompt injection.
能力标签
能力评估
Purpose & Capability
Name/description (Verilog design, testbench, simulation, VCD analysis) align with what is included: SKILL.md guidance, a simulation wrapper (simulate.sh), and a VCD-checker (check_vcd.py). No unrelated environment variables, config paths, or obscure binaries are requested.
Instruction Scope
Runtime instructions stay within the stated domain: coding style, static check with slang, running a simulator (VCS/Xrun/iverilog), generating VCDs, and analyzing VCDs with the included Python script. The only external execution steps are expected (running simulators and python3). The SKILL.md references calling the bundled check_vcd.py from a post-simulation $system call — this is consistent with automated verification but means the testbench can invoke host commands, so run only trusted testbenches.
Install Mechanism
This is instruction-only with no install spec. That's low-risk, but the reference docs and script require the Python package 'vcdvcd' (pip) and external EDA simulators (VCS/Xrun/iverilog). Those dependencies are not installed automatically by the skill; the user must provide them. No downloads from external URLs or archive extraction are present.
Credentials
No required env vars, no credentials, and no config paths are requested. Scripts use locally available commands (vcs/xrun/iverilog/python3) and local files only. This is proportionate to a simulation workflow.
Persistence & Privilege
The skill does not request persistent or platform-wide privileges; always:false and no self-enablement steps are present. It does not modify other skills or system-wide agent settings.
如何使用
- 确保已安装 OpenClaw（本地或 Docker 部署）
- 在对话框中输入安装命令：
/install verilog-design - 安装完成后，直接呼叫该 Skill 的名称或使用
/verilog-design触发 - 根据 Skill 的参数说明提供必要输入，即可获得结构化输出
版本历史
v1.2.0
**Added static syntax checking with slang to enhance design reliability.**
- Introduced a new phase for static syntax checking using slang before running simulations.
- Updated design review checklist to require slang (0 errors) before simulation.
- Clarified what slang checks for (syntax errors, type mismatches, undefined references, port errors, compliance).
- Expanded tool support in the description and throughout documentation.
- All existing flows remain; syntax check is an added mandatory step.
v1.1.0
Add support for commercial EDA simulators: Synopsys VCS and Cadence Xrun. Auto-detection with priority: VCS -> Xrun -> Icarus Verilog. Added simulate.sh helper script.
v1.0.0
Initial release of Verilog Design Flow skill.
- Provides a structured, spec-driven approach to Verilog module design, implementation, and verification.
- Includes standard coding style rules, design review checklists, and guidelines to avoid common pitfalls.
- Supplies a reusable, self-checking testbench template and simulation workflow using Icarus Verilog.
- Documents automated VCD waveform analysis options and debugging strategies.
- Details best practices for file organization, header documentation, and version tracking.
元数据
常见问题
Verilog Design Flow 是什么？
Design, implement, and verify Verilog/SystemVerilog modules with spec-driven development, self-checking testbenches, and automated simulation workflows. Supp... 它是一个面向 Claude Code / OpenClaw 的 AI Agent Skill 插件，目前累计下载 282 次。
如何安装 Verilog Design Flow？
在 OpenClaw 或 Claude Code 对话框中运行命令「/install verilog-design」即可一键安装，无需额外配置。
Verilog Design Flow 是免费的吗？
是的，Verilog Design Flow 完全免费，采用 MIT-0 许可证，可自由下载、安装和使用。
Verilog Design Flow 支持哪些平台？
Verilog Design Flow 跨平台运行，可在任意部署了 OpenClaw / Claude Code 的环境中使用（cross-platform）。
谁开发了 Verilog Design Flow？
由 billchen1020（@billchen1020）开发并维护，当前版本 v1.2.0。
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