Verilog Design Flow

Design, implement, and verify Verilog/SystemVerilog modules with spec-driven development, self-checking testbenches, and automated simulation workflows. Supp...

This skill appears coherent for Verilog simulation and VCD analysis, but take these precautions before running it: (1) Inspect testbench and RTL files you run — simulators and Verilog $system calls can execute host commands. The references show an example using $system("python3 check_vcd.py ...") which will run whatever Python is on the host. (2) Install runtime dependencies yourself (e.g., pip install vcdvcd in a virtualenv) and verify you have a trusted simulator. (3) Run simulations in a restricted/sandboxed environment if you’re running untrusted code. (4) The skill doesn’t auto-install packages or fetch remote code; if you see any attempt to download/execute from unknown URLs, treat that as suspicious.

Type: OpenClaw Skill Name: verilog-design Version: 1.2.0 The skill bundle provides a legitimate and well-structured workflow for Verilog and SystemVerilog design, simulation, and verification. It includes a bash script (scripts/simulate.sh) to automate the use of standard EDA tools like Synopsys VCS, Cadence Xrun, and Icarus Verilog, and a Python script (scripts/check_vcd.py) for waveform analysis using the 'vcdvcd' library. All instructions and code logic are strictly aligned with the stated purpose of hardware development, with no evidence of malicious intent, data exfiltration, or prompt injection.